Newfound wealth hasn't stopped him from working around the clock, he says, a bit ruefully. 他有点伤心地表示,新得到的财富并没有改变他日以继夜工作的状态。
The exposed closed-circuit cameras, the clock hanging on the balcony, and the office-style design of some of the home's elements make it a bit less-than-comfortable. 裸露的闭路摄像机、阳台上悬挂的时钟以及某些住宅元素办公风格的设计降低了别墅的舒适度。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/ D converter. 随着采样频率和A/D变换器位数的增加,时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
A new hybrid high speed clock and data recovery circuit suitable for the application in Giga bit/ s serial data communication is presented. 针对高速(Gb/s)串行数据通信应用,提出了一种混合结构的高速时钟数据恢复电路。
This paper describes the scheme of pattern transfer, the function of clock pick-up from the receiving wave, clock setting for information transmission, and how the protection equipment maintains bit synchronization. 从装置通信模块功能出发,介绍了通信码型变换方案、信息接收模块时钟提取功能,以及信息发送模块时钟选择方式。
This paper discusses the principle of DPLL and how to implement a DPLL in VHDL with a FPGA to recover bit clock from received bit stream data. 简要介绍了一种在FPGA中实现全数字锁相环(DPLL)的原理与方法,重点介绍了采用可控模数分频器实现的数字锁相环中宽频带捕获的方法与实现过程。
The hand of the century clock has already pointed to the 21st century, and human beings step into an era of information and network when atom is transformed into bit. 世纪大钟的指针已经指向了21世纪,人类踏入了一个由原子向比特转变的信息化、网络化的时代。
The performance of improved leap forward virtual clock algorithm is not destroyed seriously in especial wireless environment which has high bit error rate. 特别是在误码率很大的无线环境中,基于前跳虚时钟的调度算法性能并没有受到严重的破坏。
Clock jitter caused by various factors usually leads to sampling dots shift, decrease of the ADCs 'resolution and SNR, increase of output spectrum spur as well as bit error rate. 由各种原因引起的时钟抖动往往会引起采样点偏移,导致A/D转换器的精度和信噪比下降,使得输出信号增加不确定的频谱毛刺、增大误码率等。